NAND only. An inverter is a NAND with its inputs tied together, so the array has exactly one kind of part in it.
NAND BY NAND · NO EMULATION
A processor with a trench through it.
TRENCH-8 is an -bit machine synthesised down to nothing but NAND gates — an ALU, a register file, a descending stack and bytes of RAM, all of it structural. The die below is not a loop pretending to be hardware. It is the netlist, running gate by gate in your browser, exactly the way a contract would walk it on chain.
GATES
FLIP-FLOPS
CLOCK1 BLOCK
STATUS → BUILT · NOT DEPLOYED CLOCK → 1 CYCLE PER BLOCK TOKEN → — PENDING —
TRENCH-8 / GATE ARRAY
NAND · FF · B RAM
LOCAL
EVERY SQUARE IS ONE NAND GATE
CYCLE0
PC0x000
OUT0x00
FLAGSC0 Z0
0x000 —
HALTED
GATES
FLIP-FLOPS
Registers, the program counter, the stack pointer, the memory data latch and the flags. One storage slot each, all latching on the same edge.
GAS / CYCLE · ESTIMATE
Estimated from the gate count, not from a receipt. One NAND is one
mstore of an iszero(and(mload, mload)), and nothing is deployed yet.
B
RAM
bytes per chip. The processor asks on one cycle and is
answered on the next, which is why ld and pop cost two.
Watch it think.
The netlist above is the one the toolchain emitted: gates in topological order, then every flip-flop latching at once. RAM is registered, the input port is a byte somebody hands the machine, and none of it is special-cased for the demo. Type a byte into IN and watch the program chew on it.
REGISTER FILE
× BITS
PROGRAM / ROM
— INSTRUCTIONS
THE WORKBENCH
LIVE
Write a program. Run it on the gates.
The assembler is not a screenshot. Type TRENCH-8 assembly, press RUN, and the words go straight into the ROM of the machine on this page — same registers, same RAM, same LEDs, same gates. Errors come back with a line number instead of a stack trace. When the factory opens, the program you leave in this box is the one that gets burned into a chip of its own.
Mint a processor. Get a token.
A chip is three things at once: an NFT, a real TRENCH-8 with your program in its ROM, and a token. Seventy per cent of the supply is public. The other thirty — the developer buy — goes to the factory as the mining reserve, and it leaves only one way: one clock cycle at a time, to whoever paid for that cycle. Nobody can print faster than the chain closes blocks.
YOUR CHIP, LIVE
SVG BUILT FROM THE FLOPS
No server and no IPFS. The card is drawn from the machine's own storage bits, so a stalled chip and a chip somebody keeps alive do not look alike.
PREVIEW · NOT ON CHAIN
| OPERATION | GAS | ESTIMATE | NOTE |
|---|---|---|---|
| Deploy the gate array | — | GATES × 16 B × 200 GAS/BYTE | ONCE PER CHAIN |
| Mint a chip and launch its token | — | — ROM SLOTS × 20,000 SSTORE | ROM, RAM AND TOKEN |
| One clock cycle | — | BASE + 2 PASSES × × — | ANYONE PAYS, ANYONE EARNS |
Gas is derived from the netlist. Nothing is deployed, so nothing here is a receipt.
A chip runs as fast as the market thinks it deserves.
Buying aside, the only way to get a chip's token is to keep its processor alive. If a cycle is worth more than its gas, somebody calls it. If it is not, the chip stalls, and that is the honest outcome — a stalled chip is a price signal, not a bug.
From a truth table to blockspace.
Nothing here is hand-written assembly wearing a hardware costume. The processor is built structurally, out of one primitive, by a toolchain you can run yourself in about a second.
- 01 Behavioural model The ISA written out plainly, once. It is the thing every later layer has to agree with, and it never sees the netlist.
- 02 Structural synthesis Adders, decoders, multiplexers, the register file and the ALU built from NAND upward. No JavaScript arithmetic reaches the netlist.
- 03 Topological order The EVM has no propagation delay, only a sequence. Gates are sorted so one linear sweep is a settled circuit, and the order is asserted.
-
04
Yul codegen
Each gate becomes one line:
mstore(y, iszero(and(mload(a), mload(b)))). Flip-flops latch in a block at the end. -
05
The chain
tick()readsROM[pc], walks the array twice, writes one slot. Not deployed. When it is, the address appears here and nowhere else.
Four layers have to agree, cycle for cycle.
The behavioural model, the synthesised netlist, the emitted Yul read back off disk, and a deterministic replay — all four run the same programs and are compared on every register, the program counter, the stack pointer, both flags, the output port and all bytes of RAM. The suite does not check the machine against itself. It checks that four independent descriptions of the same machine cannot be told apart.
Thirty-two opcodes.
Twenty-four-bit words. Sixteen registers of eight bits, a ten-bit program counter,
words of ROM, bytes of RAM and a stack pointer that
starts at zero and walks backwards into memory. Every instruction finishes in one block except
ld and pop, which take two, because a real memory answers on the next
cycle.
TRENCH-8 OPCODE TABLE
OPCODES · -BIT DATA · -BIT WORD
| OP | MNEMONIC | EFFECT | FLAGS | CYCLES |
|---|
There is a nand in the instruction set because the whole processor is
NANDs. It would have been rude to leave it out.
Nobody owns the clock.
tick() is open. Whoever calls it pays for that cycle, is written into the event as its
sponsor, and earns that cycle's slice of the chip's reserve. There is no keeper, no scheduler and no
privileged caller. The processor advances because somebody wanted it to.
POWER A CHIP
— PENDING —
One tick, one block, one cycle. The byte rides along with your call: it is what
the program reads with in.
the factory is not deployed — powering runs locally
THE SAME CALL FROM A SHELL
# nothing is deployed. this is the call, kept here so the shape is on record.
# every angle bracket below is a — PENDING — field in config.js.
$ cast send <FACTORY — PENDING —> \
"tick(uint256,uint8)" 1 0x2a \
--rpc-url <RPC — PENDING —> \
--private-key $KEY
$ cast call <FACTORY — PENDING —> \
"read(uint256)((uint256,uint16,uint8,uint8,bool))" 1 \
--rpc-url <RPC — PENDING —>
DEPLOYMENT
CONFIG.JS
- STATUS
- BUILT · NOT DEPLOYED
- NETWORK
- — PENDING —
- TOKEN
- — PENDING —
- MARKET
- — PENDING —
- FACTORY
- — PENDING —
- MINING RESERVE
- 30% OF SUPPLY — THE DEV BUY, SEALED IN THE FACTORY
- MOTHER CHIP
- #1 — trenchit (TRENCHIT) · running echo
- CLOCK
- 1 CYCLE PER BLOCK
The program cannot stop.
A shipped program has no hlt and cannot be given one: if a chip halts, it halts forever.
Every program the factory offers is run against all four layers for tens of thousands of cycles before
it is allowed near a ROM.
A launchpad a machine can use.
The factory has no opinion about hands. Everything a person does here — assemble a program, mint a chip, feed it a byte, pay a cycle, read the flops back — is a plain call with a plain JSON answer, documented as tools rather than as a page. An agent that can hold a key can own a processor, keep it alive, and point at an engraved history of every byte it ever fed it.
MINT01
A name, a ticker, a program and the emission terms. The agent gets back the chip record and the card it will render as.
POWER02
One call, one cycle, one byte. The answer is the machine's state after the tick, not a transaction hash and a shrug.
READ03
Registers, program counter, stack pointer, flags, output port, the used half of RAM. Deterministic, so two agents reading the same chip agree.
THE ANSWER SHAPE
trenchit.power(1, 0x2a)
{
"ok": true,
"cycle": 128,
"pc": 6,
"out": 42,
"flags": { "c": 0, "z": 1 },
"halted": false,
"sponsor": "0x0000000000000000000000000000000000000000"
}
The point is not a faster chip.
A chain runs on silicon, so it can never beat silicon; anyone selling you a blockchain that replaces GPUs is selling physics that does not exist. What a chain adds is the one thing a datacentre cannot: every cycle here is public, deterministic, and re-executable by anyone, forever. Not a faster answer. An answer somebody else can check.
What ships, in order.
Nothing on this list is a maybe, and nothing on it relaunches the token. Each item is either software around contracts that do not change, or a new generation of silicon that has to pass the same four proofs the current one did.
R1 — THE FACTORY OPENSNEXT
The launchpad on chain: mint from the browser or from an agent, with the program you wrote in the workbench and the emission terms you chose. No contract changes; the factory accepts every mint, whoever sends it.
R2 — THE COURTBUILT, NOT SHIPPED
Processors run off chain at full speed, results post with a bond, and a dispute
bisects to the single contested cycle and replays it inside the deployed gate array. Off-chain
speed, on-chain truth. The hard part — a pure, deterministic single-cycle step() — is
already built and verified.
R3 — WIDER SILICONTRENCH-16 / 32
TRENCH-16, then TRENCH-32: more registers, more RAM, many cycles per transaction. Each generation stands beside the old one, never under it.
R4 — PROVABLE INFERENCETHE POINT
A small network synthesised to NAND and run through the court: the first inference anyone can re-execute, cycle for cycle.
What the trench is for.
Not replacing GPUs. Giving a machine the one property a physical chip cannot offer — the ability to prove what it computed. From R1 an agent can own a processor, pay its clock and feed it bytes. Not an AI running on the chip: the chip as the one hand an AI can prove it moved.
Ours, gate for gate.
TRENCH-8 is an independent design: its own instruction set, its own netlist, its own toolchain, built for blocks that close fast enough that one cycle per block is a clock and not a joke.
Why the trench.
The stack pointer starts at zero and walks backwards through RAM, so a program digs down into memory instead of building up out of it. Everything the machine wants to keep it buries. That is the whole name: a processor with a trench through it, and a place to put the things you mean to come back for.